With an increase in the memory capacity of an RAM (Random Access Memory), memory cell defect becomes a big problem. In a configuration in which all memory cells in an RAM are used, if any one of memory cells were to malfunction, the entire RAM becomes disabled. In order to cope with this, a configuration is adopted in which redundant cells, which are memory cells previously prepared as substitute for ordinarily used memory cells are provided in case any of the ordinary cells are defective memory cells. In this configuration, when a defective cell is found among the ordinary cells by a PT (Probe Test), a redundant cell is used in place of the defective cell. Such a technique has now widely been used so as to increase yield. The PT test is a test that is carried out by pressing a probe onto an electrode pad provided on each chip on the wafer. When an ordinary cell is replaced with a redundant cell, a fuse for supplying a cell selection signal is cut off.
A configuration of a conventional semiconductor memory device will be described below by separating it into a write structure and a read structure.
FIG. 8 is a block diagram showing an example of a write structure of a conventional semiconductor memory device. This semiconductor memory device includes a fuse decoder circuit 111, a memory block selection unit (MEM. BLOCK selection unit) 211, a column selection circuit (Col. Select) 311, memory blocks (MEM. BLOCK) M39, M38, . . . , M1, M0, MR, and latches WD39, WD38, . . . , WD1, WD0 for retaining write data. Each of the memory blocks has at least one memory cell. The 40 memory blocks M39, M38, . . . , M1, M0 are ordinary memory blocks, and one memory block MR is a redundant memory block (redundant MEM. BLOCK).
The memory block selection unit 211 includes 41 selectors. The selectors select an input according to corresponding control signals SR, S39, S38, . . . , S1, S0 output from the fuse decoder circuit 111 and outputs the selected input to corresponding memory blocks M39, M38, . . . , M1, M0, MR.
A selector corresponding to control signal SR selects VSS (indicating that a corresponding memory block is not used) or data of latch WD39 and writes the selected one into memory block M39. A selector corresponding to control signal S39 selects data of latch WD39 or data of latch WD38 and writes the selected one into memory block M38. Similarly, a selector corresponding to control signal S(i) (i is an integer number from 1 to 38) selects data of adjacent two latches, i.e., data of latch WD (i) or data of latch WD(i−1) and writes the selected one into memory block M(i−1) connected to the output thereof. A selector corresponding to control signal S0 selects data of latch WD0 or VSS (indicating that a corresponding memory block is not used) and writes the selected one into memory block M0.
The column selection circuit 311 selects a column corresponding to one of the memory blocks M39, M38, . . . , M1, M0, MR according to an instruction from an external device. Although not shown, the semiconductor memory device further includes a row selection circuit for selecting a row (memory cell) in each of the memory blocks M39, M38, . . . , M1, M0, MR according to an instruction from an external device.
FIG. 9 is a block diagram showing an example of a read structure of the conventional semiconductor memory device. In FIG. 9, the same reference numerals as those in FIG. 8 denote the same or corresponding parts as those in FIG. 8, and the descriptions thereof will be omitted here. As compared to the write structure shown in FIG. 8, the semiconductor memory device of FIG. 9 includes a memory block selection unit 212 in place of the memory block selection unit 211, a column selection circuit 312 in place of the column selection circuit 311, and latches RD39, RD38, . . . , RD1, RD0 for retaining read data in place of the latches WD39, WD38, . . . , WD1, WD0. The latches RD39, RD38, . . . , RD1, RD0 are connected to a scan chain in the order mentioned.
The memory block selection unit 212 includes 40 selectors. The selectors select an input according to corresponding control signals S39, S38, . . . , S1, S0 output from the fuse decoder circuit 111 and outputs the selected input to corresponding latches RD39, RD38, . . . , RD1, RD0.
A selector corresponding to control signal S39 selects data of memory block M39 and data of memory block M38 and writes the selected one into latch RD39. Similarly, a selector corresponding to control signal S(i) (i is an integer number from 0 to 38) selects data of adjacent two memory blocks, i.e., data of memory block M(i) or data of memory block M(i−1) and writes the selected one into latch RD(i) connected to the output thereof.
The column selection circuit 312 selects a column corresponding to one of the memory blocks M39, M38, . . . , M1, M0, MR. Although not shown, the semiconductor memory device further includes a row selection circuit for selecting a row in each of the memory blocks M39, M38, . . . , M1, M0, MR.
The fuse decoder circuit 111 decodes a FUSE signal from a not shown fuse circuit or an external device to generate the control signals SR, S39, S38, . . . , S1, S0, inputs the control signals SR, S39, S38, . . . , S1, S0 to respective selectors in the memory block selection unit 211 inputs the control signals S39, S38, . . . , S1, S0 to respective selectors 212 in the memory block selection unit.
In this semiconductor memory device, each of the memory blocks (ordinary memory blocks M0 to M39 constituted by ordinary cells and redundant memory block MR constituted by redundant cells) is constituted by a plurality of memory cells, and data is written into 1-bit memory cell selected by the column selection circuit 311 and row selection circuit and data is read out from 1-bit memory cell selected by the column selection circuit 312 and row selection circuit. Further, this semiconductor memory device has 1-bit redundant cell per 40-bit ordinary cell.
Operation of the semiconductor memory device at normal operation time where there is no defective cell in the ordinary memory block will be described.
At data write time, data of, e.g., latch WD39 is written into memory block M39. That is, data of latches WD39, WD38, . . . , WD1, WD0 are written into memory blocks M39, M38, . . . , M1, M0 along the paths of the memory block selection unit 211.
At data read time, data that has been written into memory block M39 is read out by latch RD39. That is, data of memory blocks M39, M38, . . . , M1, M0 are read by latches RD39, RD38, . . . , RD1, RD0 according to the operation of the memory block selection unit 212.
Operation of the semiconductor memory device at normal operation time where there is any defective cell in the ordinary memory block will be described.
Assuming that a defective cell exists in memory block M39 marked with diagonal lines in FIGS. 8 and 9, a FUSE signal specifying memory block M39 including the defective cell is input to the fuse decoder circuit 111, decoded, and then input to the memory block selection unit 211. Data of latch WD39 is written into memory block M38 through the memory block selection unit 211. That is, data of latches WD39, WD38, . . . , WD1, WD0 are written into memory blocks M38, M37, . . . , M1, M0, MR according to the operation of the memory block selection unit 211.
Similarly, a FUSE signal specifying memory block M39 including the defective cell is input to the fuse decoder circuit 111, decoded, and then input to the memory block selection unit 212. Data of memory block M38 is read out by latch RD39 through the memory block selection unit 212. That is, data of memory blocks M38, M37, . . . , M1, M0, MR are read out by latches RD39, RD38, . . . , RD1, RD0 according to the paths of the memory block selection unit 212.
The FUSE signal is generated by a not shown fuse circuit and is input to the fuse decoder circuit 111. In the case where a defective cell exists, a fuse in the fuse circuit that corresponds to the defective cell is cut off and, correspondingly, the fuse circuit generates the FUSE signal indicating the defective cell. The Fuse signal may be input from outside of the semiconductor memory device.
However, if a defect is found in the redundant cell which is supposed to relieve a defective cell, the defective cell cannot be relieved even if the fuse is cut off, resulting in a waste of man-hours. In order to avoid this, an operation test of the redundant cells is conducted before the cutting off of the fuse. In the case where an operation test of redundant cells is conducted before the cutting off of the fuse, two test methods are available.
In the first test method, an operation test of ordinary cells in which read/write operation is performed for ordinary cells is carried out in a state where there issued no indication of a defective cell by means of the FUSE signal to thereby detect a defective cell, and then a FUSE signal is given from outside so that the defective cell is switched to a redundant cell, followed by a redundant cell test in which read/write operation is performed for the redundant cells. In the second test method, an ordinary cell test is carried out first and then, irrespective of presence/absence of a defective cell, an access is forcibly made to redundant cells by means of the FUSE signal from outside to carry out a redundant cell test.
In the ordinary cell test and redundant cell test, data of latches RD39, RD38, . . . , RD1, RD0 are read out through the scan chain and then compared to data of latches WD39, WD38, . . . , WD1, WD0 that have been used for write operation, whereby it is determined whether respective cells are normal or not.
Japanese Laid-Open Patent Publication No. 08-161897 discloses a semiconductor memory device having error correction function capable of writing desired data into both data bit and redundant bit for test purpose.